1. Field of the Invention
The disclosed embodiments of the present invention relate to memory, and more particularly, to a multi-bank memory device capable of referring to a programmable latency time to continuously output data from multiple memory banks to a common data bus.
2. Description of the Prior Art
A conventional memory utilizes data registers (FIFO) for temporary storage of data due to access latency. Please refer to FIG. 1, which is a block diagram illustrating a conventional dynamic random access memory (DRAM) 100. A shown in FIG. 1, a control circuit 104 controls each of a plurality of decoders (DEC) 110_1-110_3 to decode an address signal ADD according to an access signal ACS (a clock signal), and data read from a plurality of memory cell arrays 106_1-106_3 are transmitted to a plurality of sense amplifiers 120_1-120_3 through a plurality of data paths SA1-SA3, respectively. Next, the sense amplifiers 120_1-120_3 immediately transmit the data read from the memory cell arrays 106_1-106_3 to data register(s) 130 (e.g. a first-in first-out register (FIFO)) through a common data bus 160 (which is shared by a plurality of memory banks 102_1-102_3), and an off-chip driver (OCD) 140 of an output circuit 132 receives an output of the data register(s) (FIFO) 130 to generate a data output DQ, wherein data output timing of the data register(s) (FIFO) 130 is controlled by the control circuit 104. Additionally, in a write mode, an input buffer 150 of the output circuit 132 receives data to be written, and transmits the data to be written to the data register(s) (FIFO) 130 through the common data bus 160.
FIG. 2 illustrates a timing diagram of the DRAM 100 shown in FIG. 1 which operates in a burst mode to access the same memory bank continuously. For illustrative purposes, a plurality of rising edges of the access signal ACS are labeled R0-R15 in FIG. 2. At the rising edge R0, the memory bank 102_1 enables data access according to an output of the DEC 110_1. After a period of time (an address access time (tAA)), data D0-D3 are read from the memory cell array 106_1 to the data path SA1 (at a time point between the rising edge R4 and the rising edge R5), and the sense amplifier 120_1 transmits the data D0-D3 to the data register(s) (FIFO) 130 through the common data bus 160. As the DRAM 100 has a read latency of 9 clock cycles, the data D0-D3 are outputted from the OCD 140 at the rising edges R9-R12 respectively. Similarly, data D4-D5 read from the memory cell array 106_2 are outputted from the OCD 140 at the rising edges R13-R14 respectively, and data D6-D7 read from the memory cell array 106_3 are outputted from the OCD 140 at the rising edges R15-R15 respectively.
As can be seen from FIG. 1 and FIG. 2, a first-in first-out register is used to buffer continuous burst data before a long column address strobe (CAS) latency is satisfied. However, this causes an increase in circuit area and manufacturing costs. Similar problems are also encountered when data are read out from different memory banks of the DRAM 100 in sequence.